1. Field of the Invention
The present invention relates to a static-type master-slave flip-flop circuit.
2. Description of the Prior Art
With the advancement of micromachining and related technologies, LSIs (large-scale integrated circuits) have come to offer increasingly high operation speeds and increasingly high degrees of integration. To make high-speed LSIs commercially viable, it is essential to minimize their power consumption. This is because the higher the speed at which an LSI operates, the higher its power consumption, and, to stabilize its operation, it becomes necessary to provide it with some heat dissipation means such as a ceramic package or heat radiating fins. Inconveniently, this requires extra cost.
Moreover, in those small-size and light-weight portable appliances that have been gaining popularity in recent years, reduction of power consumption is essential also from the viewpoint of the duration of the battery by which they are powered. In particular, with flip-flop circuits operating at high speeds, which are prone to extremely high power consumption, it is advisable to adopt circuit designs that minimize power consumption.
Conventionally, static-type master-slave flip-flop circuits that employ CMOS FETs (complementary metal-oxide semiconductor field-effect transistors) are widely used for their high-speed operation and comparatively low power consumption. FIG. 8 shows an example of such a conventional static-type master-slave flip-flop circuit. How this flip-flop circuit is configured and how it operates will be described below.
In FIG. 8, D represents a data input signal, CK represents a clock input signal, and Q represents a data output signal. The clock signal CK that has been fed to the flip-flop circuit is first inverted by the inverter circuit 200 to produce a signal CKX, which is then once again inverted by the inverter circuit 201 to produce a signal CK1. The signals CKX and CK1 are applied to the transfer gates 202, 205, 206, and 209 to turn them on/off in an appropriate manner.
FIG. 9 is a diagram illustrating the configuration of one of those transfer gates on the level of its constituent transistors. The transfer gate is composed of an N-channel MOS FET (hereafter referred to simply as an xe2x80x9cNMOS transistorxe2x80x9d) 210 and a P-channel MOS FET (hereafter referred to simply as a xe2x80x9cPMOS transistorxe2x80x9d) 211 connected in parallel. The NMOS and PMOS transistors 210 and 211 are turned on/off by receiving at their gates the signals CK and CKX respectively, which are inverted with respect to each other.
For example, when the signal CK is at a high level and the signal CKX is at a low level, the NMOS and PMOS transistors 210 and 211 are both turned on, connecting the two ends A and Y of the transfer gate to each other. On the other hand, when the signal CK is at a low level and the signal CKX is at a high level, the NMOS and PMOS transistors 210 and 211 are both turned off, disconnecting the two ends A and Y of the transfer gate from each other.
In the circuit shown in FIG. 8, when the clock input signal CK is at a low level, the inverter circuits 200 and 201 turn the signal CKX to a high level and turn the signal CK1 to a low level. This turns the transfer gate 202 on, and thus the master latch delivers the data input signal D to the node 220. When the data input signal D is at a low level, the inverter circuit 203 turns the level at the node 221 to a high level, and the inverter circuit 204 turns the level at the node 222 to a low level. At this time, the transfer gates 205 and 206 remain off, and thus the data delivered to the master latch is not transferred to the slave latch.
Next, when the clock signal CK turns to a high level, the inverter circuits 200 and 201 turn the signal CKX to a low level and turn the signal CK1 to a high level. This turns the transfer gate 202 off and turns the transfer gates 205 and 206 on. Thus, in the master latch, the data fed thereto is held by the inverter circuits 203 and 204 and the transfer gate 205.
Moreover, the transfer gate 206 thus turned on causes the signal present at the node 221 to be delivered to the node 223 of the slave latch. Thus, the inverter circuit 207 turns the data output signal Q to a low level, and the inverter circuit 208 turns the level at the node 224 to a high level. At this time, the transfer gate 209 remains off.
Next, when the clock signal CK turns to a low level, the transfer gate 206 is turned off, and the transfer gate 209 is turned on. Thus, in the slave latch, the data is held so that the data output signal Q will be kept at a low level.
In this way, when the clock signal CK is at a low level, the data input signal D is fed to the master latch, and, when the clock signal CK turns to a high level, the data is transferred to the slave latch, causing the data output signal Q to be output. Thereafter, when the clock signal CK turns back to a low level, the slave latch holds the data output signal Q. In a similar manner, when the data input signal D is at a high level, a high level is output as the data output signal Q.
However, in this conventional flip-flop circuit (FIG. 8), every time the clock signal CK changes its level, and regardless of the level of the data input signal D, currents flow to charge/discharge the gate capacitors in the six PMOS and six NMOS transistors constituting the inverter circuits 200 and 201 and the transfer gates 202, 205, 206, and 209 as well as the drain capacitors within the inverter circuits 200 and 201.
Moreover, in the inverter circuits 200 and 201, which are each composed of a PMOS transistor and an NMOS transistor connected in series, there appears, just when the clock input signal CK changes its level, a period in which the PMOS and NMOS transistors are both kept on simultaneously. During this period, a current (called a through current) flows from the supplied voltage directly to ground GND, increasing power consumption.
Furthermore, as shown in FIG. 10, a PMOS transistor is on when its gate voltage is in a range R1 lower than a voltage VDDxe2x88x92VthP, which equals to its threshold voltage VthP subtracted from the supplied voltage VDD; on the other hand, an NMOS transistor is on when its gate voltage is in a range R2 higher than its threshold voltage Vthn.
For example, in any of the above-mentioned inverter circuits, before the clock signal fed thereto starts rising, i.e. when it is at a low level, the PMOS transistor is on and the NMOS transistor is off. When the clock signal reaches the voltage Vthn, the NMOS transistor, which receives the clock signal at its gate, is turned on. When the clock signal reaches the voltage VDDxe2x88x92VthP, the PMOS transistor is turned off.
Thus, while the signal CKX is rising, there appears, starting when the signal CKX reaches the voltage Vthn and ending when it reaches the voltage VDDxe2x88x92VthP, a period in which the NMOS transistor of the transfer gate 202 and the PMOS transistor of the transfer gate 205 are both kept on simultaneously. Similarly, while the signal CK1 is falling, there appears a period in which the PMOS transistor of the transfer gate 202 and the NMOS transistor of the transfer gate 205 are kept on simultaneously.
As a result, when the data that is to be received next happens to be contrary to the data already held in the master latch, a through current flows through the transfer gates 202 and 205 between the data input signal D and the output of the inverter circuit 204. Similarly, also when data is fed from the master latch to the slave latch, if the output of the inverter circuit 203 is contrary to the output of the inverter circuit 208, a through current flows through the transfer gates 206 and 209.
Moreover, the signals CKX and CK1, which are produced by the inverter circuits 200 and 201, have a phase difference, which prevents the transfer gates 202 and 205 from being turned on/off simultaneously at all times. This causes a through current to flow through the transfer gates 202 and 205 when the data input signal D is contrary to the output of the inverter circuit 204.
Furthermore, this conventional flip-flop circuit (FIG. 8) operates on the signals CKX and CK1 that it produces by the use of the inverter circuits 200 and 201 from the clock signal CK it receives. That is, this flip-flop circuit operates with a delay with respect to the clock input signal CK it receives, and therefore it requires, at trailing edges of the clock input signal CK, a sufficiently long data hold time to ensure that data is held securely in the master latch.
An object of the present invention is to provide a CMOS flip-flop circuit that operates with markedly low power consumption.
To achieve the above object, according to one aspect of the present invention, a static CMOS flip-flop circuit is composed of a master latch and a slave latch and operates on a data input signal and a clock input signal fed thereto. Here, the master latch has: a data input circuit that, when the clock input signal is at a first level, reads the data input signal; a first data holding circuit that, when the clock input signal is at a second level, holds the data read by the data input circuit; and a signal switching circuit that, when the clock input signal is at the first level, outputs a predetermined level and that, when the clock input signal is at the second level, outputs the data held by the first data holding circuit after inverting it. On the other hand, the slave latch has: a data output circuit that, when the clock input signal is at the second level, reads an output of the signal switching circuit after inverting it; and a second data holding circuit that, when the clock input signal is at the first level, holds the data read by the data output circuit.
Configured as described above, this flip-flop circuit reads the data input signal by the use of the data input circuit provided in the master latch when the clock input signal is at a first, e.g. low, level. Irrespective of the level of the data, the signal switching circuit outputs a predetermined, e.g. high, level. This inhibits the operation of the data output circuit in the slave latch, and thus the data is not transferred. Next, when the clock input signal changes to a second, e.g. high, level, the master latch activates the first data holding circuit to hold the data read by the data input circuit. Then, the signal switching circuit outputs the data held in the first data holding circuit after inverting it. While the clock input signal is at the second level, the slave latch reads, by the use of the data output circuit, the output of the signal switching circuit after inverting it. When the clock input signal changes back to the first level, the data thus read is held by the second data holding circuit. In this way, the output signal of the flip-flop circuit is obtained. Then, the master latch reads new data, and thus the flip-flop circuit operates in synchronism with the input signal. In this way, the output of the flip-flop circuit is kept stable.